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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. opa2810 sbos789a ? august 2017 ? revised june 2018 opa2810 dual channel, 27 v, rail-to-rail input/output fet-input operational amplifier 1 1 features 1 ? gain-bandwidth product: 70 mhz ? small-signal bandwidth: 105 mhz ? slew rate: 192 v/ s ? wide supply range: 4.75 v to 27 v ? low noise: ? input voltage noise: 6 nv/ hz (f = 500 khz) ? input current noise: 5 fa/ hz (f = 10 khz) ? rail-to-rail input and output: ? fet input stage: 2 pa input bias current (typical) ? high linear output current: 75 ma ? input offset: 1.5 mv (maximum) ? offset drift: 2 v/ c (typical) ? low power: 3.6 ma/channel ? extended temperature operation: ? 40 c to +125 c 2 applications ? wideband photodiode transimpedance amplifiers ? high-z front-ends ? impedance measurements ? power analyzers ? multichannel sensor interface ? level shifting and buffering ? optoelectronic drivers multichannel sensor interface 3 description the opa2810 is a dual-channel, fet-input, voltage- feedback operational amplifier with low input bias current. the opa2810 is unity-gain stable with a small-signal unity-gain bandwidth of 105 mhz, and offers excellent dc precision and dynamic ac performance at a low quiescent current (i q ) of 3.6 ma per channel (typical). the opa2810 is fabricated on texas instrument's proprietary, high-speed sige bicmos process and achieves significant performance improvements over comparable fet- input amplifiers at similar levels of quiescent power. with a gain-bandwidth product (gbwp) of 70 mhz, slew-rate of 192 v/ s, and voltage low-noise of 6 nv/ hz, the opa2810 is well suited for use in a wide range of high fidelity data acquisition and signal processing applications. the opa2810 is characterized to operate over a wide supply range of 4.75 v to 27 v, and features rail-to- rail inputs and outputs. the opa2810 amplifier delivers 75 ma of linear output current, suitable for driving optoelectronics components and analog-to- digital converter (adc) inputs or buffering dac outputs into heavy loads. the opa2810 is available in an 8-pin, sot23-8 and vssop-8 package and is rated to work over the extended industrial temperature range of ? 40 c to +125 c. device information (1) part number package body size (nom) opa2810 sot-23 (8) 2.90 mm 1.60 mm vssop (8) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. harmonic distortion vs frequency mux + adc opa2810 frequency (hz) harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 100k 1m d048 hd2, r l = 1 k : hd3, r l = 1 k : hd2, r l = 500 : hd3, r l = 500 : tools & software technical documents ordernow productfolder support &community
2 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics: 10 v ................................. 5 6.6 electrical characteristics: 24 v ................................. 8 6.7 electrical characteristics: 5 v ................................. 11 6.8 typical characteristics: v s = 10 v .......................... 14 6.9 typical characteristics: v s = 24 v .......................... 17 6.10 typical characteristics: v s = 5 v .......................... 20 6.11 typical characteristics: 2.375 v to 12 v split supply ...................................................................... 22 7 detailed description ............................................ 25 7.1 overview ................................................................. 25 7.2 functional block diagram ....................................... 25 7.3 feature description ................................................. 27 7.4 device functional modes ........................................ 27 8 application and implementation ........................ 28 8.1 application information ............................................ 28 8.2 typical applications ............................................... 33 9 power supply recommendations ...................... 36 10 layout ................................................................... 36 10.1 layout guidelines ................................................. 36 10.2 layout example .................................................... 37 10.3 thermal considerations ........................................ 38 11 device and documentation support ................. 39 11.1 documentation support ........................................ 39 11.2 receiving notification of documentation updates 39 11.3 community resources .......................................... 39 11.4 trademarks ........................................................... 39 11.5 electrostatic discharge caution ............................ 39 11.6 glossary ................................................................ 39 12 mechanical, packaging, and orderable information ........................................................... 39 4 revision history changes from original (august 2017) to revision a page ? changed device status from advance information to production data ................................................................................. 1
3 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 5 pin configuration and functions dcn and dgk packages 8-pin sot-23 and vssop top view (1) i = input, o = output, and p = power. pin functions pin type (1) description name no. vo1 1 o amplifier 1 output pin vin1- 2 i amplifier 1 inverting input pin vin1+ 3 i amplifier 1 noninverting input pin vs- 4 p negative power supply pin vin2+ 5 i amplifier 2 noninverting input pin vin2- 6 i amplifier 2 inverting input pin vo2 7 o amplifier 2 output pin vs+ 8 p positive power supply pin 1 vo1 8 vs+ 2 vin1- 7 vo2 3 vin1+ 6 vin2- 4 vs- 5 vin2+ not to scale
4 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) v s is the total supply voltage given by v s = v s+ ? v s ? . (3) equal to the lower of 7 v or total supply voltage. (4) long-term continuous output current for electromigration limits. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v s supply voltage (total bipolar supplies) (2) 14 v v in input voltage v s ? ? 0.5 v s+ + 0.5 v v in,diff differential input voltage (3) 7 v i i continuous input current 10 ma i o continuous output current (4) t a = ? 40 to +85 40 ma t a = 125 12 ma p d continuous power dissipation see thermal information t j junction temperature 150 c t stg storage temperature ? 65 125 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2500 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 1500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v s total supply voltage 4.75 27 v t a ambient temperature ? 40 25 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) opa2810 unit dcn (sot-23) dgk (vssop) 8 pins 8 pins r ja junction-to-ambient thermal resistance 130.9 177.2 c/w r jc(top) junction-to-case (top) thermal resistance 86.6 64.6 c/w r jb junction-to-board thermal resistance 42.3 99.0 c/w jt junction-to-top characterization parameter 25.9 9.7 c/w jb junction-to-board characterization parameter 42.3 97.3 c/w r jc(bot) junction-to-case (bottom) thermal resistance ? ? c/w
5 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) for ac specifications, g = 2 v/v, r f = 1 k ? and c l = 4.7 pf (unless otherwise noted). (2) test levels (all values set by characterization and simulation): (a) 100% tested at 25 c, overtemperature limits by characterization and simulation; (b) not tested in production, limits set by characterization and simulation; (c) typical value only for information. (3) lower of the measured positive and negative slew rate. 6.5 electrical characteristics: 10 v test conditions unless otherwise noted: t a = 25 c, v s+ = 5 v, v s ? = ? 5 v, r l = 1 k , input and output are biased to midsupply (1) . parameter test conditions min typ max unit test level (2) ac performance ssbw small-signal bandwidth g = 1, v o = 20 mv pp , r f = 0 ? 75 mhz c g = 1, v o = 20 mv pp , r f = 0 ? , c l = 33 pf 105 mhz c g = ? 1, v o = 20 mv pp 50 mhz c g = 2, v o = 20 mv pp 49 mhz c g = 5, v o = 20 mv pp 15 mhz c lsbw large-signal bandwidth g = 2, v o = 2 v pp 38 mhz c g = 2, v o = 4 v pp 26 mhz c gbwp gain-bandwidth product g = 11, v o = 20 mv pp 70 mhz c bandwdith for 0.1db flatness g = 2, v o = 20 mv pp 13 mhz c sr slew rate (20%-80%) (3) g = 2, v o = ? 2-v to 2-v step 192 v/ s c g = ? 1, v o = ? 2-v to 2-v step 187 v/ s c g = 2, v o = ? 4.5-v to 3.5-v step 193 v/ s c rise time v o = 200-mv step 4 ns c fall time v o = 200-mv step 5 ns c settling time to 0.1% g = 2, v o = 2-v step 73 ns c g = 2, v o = 8-v step 97 ns c g = ? 1, v o = 8-v step 96 ns c settling time to 0.001% g = 2, v o = 2-v step 374 ns c g = 2, v o = 8-v step 213 ns c g = ? 1, v o = 8-v step 163 ns c overshoot/undershoot g = +1, r f = 0 ? , v o = 200 mv pp 9/10 % c g = +1, r f = 0 ? , v o = 2 v pp 4/5 % c input overdrive recovery g = 1, r f = 0 ? , (v s ? ? 0.5 v) to (v s+ + 0.5 v) input (see figure 14 ) 44 ns c output overdrive recovery g = ? 1, (v s ? ? 0.5 v) to (v s+ + 0.5 v) input (see figure 15 ) 55 ns c hd2 second-order harmonic distortion f = 100 khz, r l = 1 k , v o = 2 v pp ? 118 dbc c f = 100 khz, r l =1 k , v o = 8 v pp ? 101 dbc c f = 1 mhz, r l = 1 k , v o = 2 v pp ? 99 dbc c f = 1 mhz, r l =1 k , v o = 8 v pp ? 82 dbc c hd3 third-order harmonic distortion f = 100 khz, r l = 1 k , v o = 2 v pp ? 134 dbc c f = 100 khz, r l = 1 k , v o = 8 v pp ? 105 dbc c f = 1 mhz, r l = 1 k , v o = 2 v pp ? 104 dbc c f = 1 mhz, r l = 1 k , v o = 8 v pp ? 92 dbc c e n input-referred voltage noise f = 500 khz, flatband 6 nv/ hz c f = 0.1-10 hz integrated 0.42 vrms c e i input-referred current noise f = 10 khz 5 fa/ hz c z o close-loop output impedance f = 100 khz 0.007 c
6 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics: 10 v (continued) test conditions unless otherwise noted: t a = 25 c, v s+ = 5 v, v s ? = ? 5 v, r l = 1 k , input and output are biased to midsupply (1) . parameter test conditions min typ max unit test level (2) (4) maximum bias current specification is set using 5 limits (corresponding to 0.58 dppm) obtained using the statistical distribution from electrical characterization over temperature of a sample set of 70 units. maximum specification is not specified by final automated test equipment (ate) nor by qa sample testing. (5) change in input offset from its value when input is biased to midsupply. dc performance a ol open-loop voltage gain f = dc, v o = 2.5 v 108 120 db a t a = ? 40 c to +125 c 108 b v os input offset voltage t a = 25 c 0.1 1.5 mv a t a = ? 40 c to +85 c 2.4 mv b t a = ? 40 c to +125 c 2.8 mv b input offset voltage drift t = 25 c 1.5 v/ c b t a = ? 40 c to +125 c 13 v/ c b input bias current t a = 25 c 2 20 pa a t a = ? 40 c to +85 c (4) 20 60 pa b t a = ? 40 c to +125 c (4) 100 350 pa b input offset current t a = 25 c 1 20 pa a t a = ? 40 c to +85 c 5 pa b t a = ? 40 c to +125 c 50 pa b cmrr common-mode rejection ratio f = dc, t a = 25 c, v cm = ? 3 v to +1 v 85 100 db a t a = ? 40 c to +125 c 85 db b input allowable input differential voltage see figure 57 7 v c common-mode input impedance in closed-loop configuration 12 || 2.5 g ||pf c differential input capacitance in open-loop configuration 0.5 pf c most positive input voltage v os < 5 mv (5) v s+ + 0.2 v s+ + 0.3 v a t a = ? 40 c to +125 c v s+ + 0.2 v b most negative input voltage v os < 5 mv (5) v s ? ? 0.2 v s ? ? 0.3 v a t a = ? 40 c to +125 c v s ? ? 0.2 v b most positive input voltage for main-jfet stage t = 25 c (see figure 18 ) v s+ ? 2.9 v s+ ? 2.5 v c t a = ? 40 c to +125 c v s+ ? 3 v c output v ocrh output voltage range high t a = 25 c, r l = 667 v s+ ? 0.18 v s+ ? 0.11 v a t a = ? 40 c to +125 c, r l = 667 v s+ ? 0.2 v b v ocrl output voltage range low t a = 25 c, r l = 667 v s ? + 0.15 v s ? + 0.08 v a t a = ? 40 c to +125 c, r l = 667 v s ? + 0.2 v b i o(max) linear output drive (sourcing and sinking) t a = 25 c, v o = 2.65 v, r l = 51 , v os < 2 mv 52 75 ma a t a = ? 40 c to +125 c, v o = 2.65v, r l = 51 , v os < 2 mv 40 ma b i sc output short-circuit current t a = 25 c, t delay = 5 ms 95 100 ma b c l capacitive load drive < 1 db peaking, r s = 0 ? 35 pf c
7 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics: 10 v (continued) test conditions unless otherwise noted: t a = 25 c, v s+ = 5 v, v s ? = ? 5 v, r l = 1 k , input and output are biased to midsupply (1) . parameter test conditions min typ max unit test level (2) (6) change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +psrr and -psrr. power supply v s operating voltage t a = 25 c 4.75 27 v a t a = ? 40 c to +125 c 4.75 27 v b i q quiescent current per channel t a = 25 c 3.125 3.6 4.05 ma a t a = ? 40 c to +125 c 2.9 4.4 ma b psrr power supply rejection ratio v s = 2 v (6) 82 100 db a t a = ? 40 c to +125 c 82 db b auxiliary cmos input stage gain-bandwidth product v cm = (v s+ ) ? 1 v 35 mhz c open-loop voltage gain v cm = (v s+ ) ? 1 v, f = dc, v o = 2 v to 4 v 80 100 db a input-referred voltage noise v cm = v s+ ? 1v, f = 1 mhz 21 nv/ hz c input offset voltage v cm = v s+ ? 1.5 v, no-load 4 mv a v cm = v s+ ? 0.5 v, no-load 4.8 mv a v cm = v s+ ? 0.5 v, t a = ? 40 c to +125 c, no-load 6.4 mv b input bias current v cm = v s+ ? 1.5 v 2 20 pa a v cm = v s+ ? 1.5 v, t a = -40 c to +125 c 0.15 0.5 na b common-mode rejection ratio v cm = v s+ - 1.5 v to v s+ ? 0.5 v 75 db b power supply rejection ratio v cm = v s+ ? 1.5 v, v s = 2 v (6) 75 db b channel matching channel-to-channel gbwp mismatch t a = 25 c 3 % c channel-to-channel crosstalk f = 100 khz ? 93 dbc c input offset voltage mismatch t a = 25 c 0.1 2.5 mv a
8 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) for ac specifications, g = 2 v/v, r f = 1 k ? and c l = 4.7 pf (unless otherwise noted). (2) test levels (all values set by characterization and simulation): (a) 100% tested at 25 c, overtemperature limits by characterization and simulation; (b) not tested in production, limits set by characterization and simulation; (c) typical value only for information. (3) lower of the measured positive and negative slew rate. 6.6 electrical characteristics: 24 v test conditions unless otherwise noted: t a = 25 c, v s+ = 12 v, v s ? = ? 12 v, r l = 1 k , input and output are biased to midsupply (1) . parameter test conditions min typ max unit test level (2) ac performance ssbw small-signal bandwidth g = 1, v o = 20 mv pp , r f = 0 ? 75 mhz c g = 1, v o = 20 mv pp , r f = 0 ? , c l = 33 pf 105 mhz c g = ? 1, v o = 20 mv pp 51 mhz c g = 2, v o = 20 mv pp 49 mhz c g = 5, vo = 20 mv pp 15 mhz c lsbw large-signal bandwidth g = 2 v o = 2 v pp 38 mhz c g = 2 v o = 10 v pp 14 mhz c gbwp gain-bandwidth product g = 11, v o = 20 mv pp 70 mhz c bandwdith for 0.1db flatness g = 2, v o = 20 mv pp 12 mhz c sr slew rate (20%-80%) (3) g = 2, v o = ? 2-v to 2-v step 226 v/ s c g = ? 1, v o = ? 2-v to 2-v step 218 v/ s c g = 2, v o = ? 4.5-v to 3.5-v step 243 v/ s c rise time v o = 200-mv step 4 ns c fall time v o = 200-mv step 5 ns c settling time to 0.1% g = 2, v o = 2-v step 72 ns c g = 2, v o = 10-v step 90 ns c g = ? 1, v o = 10-v step 89 ns c settling time to 0.001% g = 2, v o = 2-v step 370 ns c g = 2, v o = 10-v step 210 ns c g = ? 1, v o = 10-v step 150 ns c overshoot/undershoot g = 1, r f = 0 ? , v o = 200 mv pp 7.5/9 % c g = 1, r f = 0 ? , v o = 2 v pp 4/5 % c input overdrive recovery g = 1, r f = 0 ? , (v s ? ? 0.5 v) to (v s+ + 0.5 v) input (see figure 31 ) 66 ns c output overdrive recovery g = ? 1, (v s ? ? 0.5 v) to (v s+ + 0.5 v) input (see figure 32 ) 30 ns c hd2 second-order harmonic distortion f = 100 khz, r l = 1 k , v o = 2 v pp ? 123 dbc c f = 100 khz, r l =1 k , v o = 10 v pp ? 113 dbc c f = 1 mhz, r l = 1 k , v o = 2 v pp ? 105 dbc c f = 1 mhz, rl=1 k , v o = 10 v pp ? 92 dbc c hd3 third-order harmonic distortion f = 100 khz, r l = 1 k , v o = 2 v pp ? 134 dbc c f = 100 khz, r l =1 k , v o = 10 v pp ? 130 dbc c f = 1 mhz, r l = 1 k , v o = 2 v pp ? 103 dbc c f = 1 mhz, r l =1 k , v o = 10 v pp ? 86 dbc c e n input-referred voltage noise f = 500 khz, flatband 6 nv/ hz c f = 0.1-10 hz integrated 0.36 vrms c e i input-referred current noise f = 10 khz 5 fa/ hz c z o close-loop output impedance f = 100 khz 0.007 c
9 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics: 24 v (continued) test conditions unless otherwise noted: t a = 25 c, v s+ = 12 v, v s ? = ? 12 v, r l = 1 k , input and output are biased to midsupply (1) . parameter test conditions min typ max unit test level (2) (4) maximum bias current specification is set using 5 limits (corresponding to 0.58 dppm) obtained using the statistical distribution from electrical characterization over temperature of a sample set of 70 units. maximum specification is not specified by final automated test equipment (ate) nor by qa sample testing. (5) change in input offset from its value when input is biased to midsupply. dc performance a ol open-loop voltage gain f = dc, v o = 8 v 108 120 db a t a = ? 40 c to +125 c 108 db b v os input offset voltage t a = 25 c 0.1 1.5 mv a t a = ? 40 c to +85 c 2.4 mv b t a = ? 40 c to +125 c 2.8 mv b input offset voltage drift t a = 25 c 1.5 v/ c b t a = ? 40 c to +125 c 13 v/ c b input bias current t a = 25 c 2 20 pa a t a = ? 40 c to +85 c (4) 20 60 pa b t a = ? 40 c to +125 c (4) 100 460 pa b input offset current t a = 25 c 1 20 pa a t a = ? 40 c to +85 c 5 pa b t a = ? 40 c to +125 c 50 pa b cmrr common-mode rejection ratio f = dc, t a = 25 c, v cm = 5 v 90 105 db a t a = ? 40 c to +125 c 90 db b input allowable input differential voltage see figure 57 7 v c common-mode input impedance in closed-loop configuration 12 || 2.5 g ||pf c differential input capacitance in open-loop configuration 0.5 pf c most positive input voltage v os < 5 mv (5) v s+ + 0.2 v s+ + 0.3 v a t a = ? 40 c to +125 c v s+ + 0.1 v b most negative input voltage v os < 5 mv (5) v s ? ? 0.2 v s ? ? 0.3 v a t a = ? 40 c to +125 c v s ? ? 0.2 v b most positive input voltage for main-jfet stage t a = 25 c (see figure 35 ) v s+ ? 2.9 v s+ ? 2.5 v c t a = ? 40 c to +125 c v s+ ? 3 v c output v ocrh output voltage range high t a = 25 c, r l = 667 v s+ ? 0.33 v s+ ? 0.22 v a t a = ? 40 c to +125 c, r l = 667 v s+ ? 0.36 v b v ocrl output voltage range low t a = 25 c, r l = 667 v s ? + 0.23 v s ? + 0.15 v a t a = ? 40 c to +125 c, r l = 667 v s ? + 0.33 v b i o(max) linear output drive (sourcing and sinking) t a = 25 c, v o = 7.25 v, r l = 151 , v os < 2 mv 48 64 ma a t a = ? 40 c to +90 c, v o = 7.25v, r l = 151 , v os < 2 mv 40 ma b i sc output short-circuit current t a = 25 c, t delay = 5 ms 101 108 ma b c l capacitive load drive < 1 db peaking, r s = 0 ? 35 pf c
10 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics: 24 v (continued) test conditions unless otherwise noted: t a = 25 c, v s+ = 12 v, v s ? = ? 12 v, r l = 1 k , input and output are biased to midsupply (1) . parameter test conditions min typ max unit test level (2) (6) change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +psrr and -psrr. power supply vs operating voltage t a = 25 c 4.75 27 v a t a = ? 40 c to +125 c 4.75 27 v b i q quiescent current per channel t a = 25 c 3.2 3.7 4.1 ma a t a = ? 40 c to +125 c 3.0 4.5 ma b psrr power supply rejection ratio v s = 2 v (6) 90 105 db a t a = ? 40 c to +125 c 90 db b auxiliary cmos input stage gain-bandwidth product v cm = v s+ ? 1 v 35 mhz c open-loop voltage gain v cm = v s+ ? 1 v, f = dc, v o = 7 v to ? 7 v 80 95 db a input-referred voltage noise v cm = v s+ ? 1 v, f = 1 mhz 21 nv/ hz c input offset voltage v cm = v s+ ? 1.5 v, no-load 4 mv a v cm = v s+ ? 0.5 v, no-load 4.8 mv a v cm = v s+ ? 0.5 v, t a = ? 40 c to +125 c, no-load 6.4 mv b input bias current v cm = v s+ ? 1.5 v 2 24 pa a v cm = v s+ ? 1.5 v, t a = ? 40 c to +125 c 0.15 1 na b common-mode rejection ratio v cm = v s+ ? 1.5 v to v s+ ? 0.5 v 75 db b power supply rejection ratio v cm = v s+ ? 1.5 v, v s = 2 v (6) 70 db b channel matching channel-to-channel gbwp mismatch t a = 25 c 3 % c channel-to-channel crosstalk f = 100 khz -93 dbc c input offset voltage mismatch t a = 25 c 0.1 2.5 mv a
11 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated (1) for ac specifications, v s+ = 3.5 v, v s ? = ? 1.5 v, g = 2 v/v, r f = 1 k ? , c l = 4.7 pf, input and output are biased to 0 v (unless otherwise noted). (2) test levels (all values set by characterization and simulation): (a) 100% tested at 25 c, overtemperature limits by characterization and simulation; (b) not tested in production, limits set by characterization and simulation; (c) typical value only for information. (3) lower of the measured positive and negative slew rate. 6.7 electrical characteristics: 5 v test conditions unless otherwise noted: t a = 25 c, v s+ = 5 v, v s ? = 0 v, v cm = 1.25 v, r l = 1 k , and output is biased to midsupply (1) . parameter test conditions min typ max unit test level (2) ac performance ssbw small-signal bandwidth g = 1, v o = 20 mv pp , r f = 0 ? 74 mhz c g = 1, v o = 20 mv pp , r f = 0 ? , c l = 33 pf 103 mhz c g = ? 1, v o = 20 mv pp 51 mhz c g = 2, v o = 20 mv pp 49 mhz c g = 5, v o = 20 mv pp 15 mhz c lsbw large-signal bandwidth g = 2 v o = 2 v pp 33 mhz c gbwp gain-bandwidth product g = 11, v o = 20 mv pp 70 mhz c bandwdith for 0.1db flatness g = 2, v o = 20 mv pp 11 mhz c sr slew rate (20%-80%) (3) g = 2, v o = ? 1-v to 1-v step 119 v/ s c g = 2, v o = ? 2-v to 2-v step, v s = 2.5 v 88 v/ s c rise time v o = 200-mv step 4 ns c fall time v o = 200-mv step 5 ns c settling time to 0.1% g = 2, v o = ? 2-v to 0-v step, v s = 2.5 v 108 ns c settling time to 0.001% g = 2, v o = ? 2-v to 0-v step, v s = 2.5 v 197 ns c overshoot/undershoot g = 1, v o = 200 mv pp 10/11 % c g = 1, v o = ? 1.25-v to 0.75-v step 1/7 % c input overdrive recovery g = 1, (v s ? ? 0.5 v) to (v s+ + 0.5 v) input, v s = 2.5 v (see figure 39 ) 71 ns c output overdrive recovery g = ? 1, (v s ? ? 0.5 v) to (v s+ + 0.5 v) input, v s = 2.5 v (see figure 40 ) 91 ns c hd2 second-order harmonic distortion f = 100 khz, r l = 1 k , v o = 2 v pp ? 102 dbc c f = 1 mhz, r l = 1 k , v o = 2 v pp ? 85 dbc c hd3 third-order harmonic distortion f = 100 khz, r l = 1 k , v o = 2 v pp ? 113 dbc c f = 1 mhz, r l = 1 k , v o = 2 v pp ? 97 dbc c e n input-referred voltage noise f = 500 khz, latband 6 nv/ hz c f = 0.1-10 hz integrated 0.42 vrms c e i input-referred current noise f = 10 khz 5 fa/ hz c z o close-loop output impedance f = 100 khz 0.007 c dc performance a ol open-loop voltage gain f = dc, v o = 1.25 v to 3.25 v 104 118 db a t a = ? 40 c to +125 c 104 db b v os input offset voltage t a = 25 c, no-load 0.1 1.5 mv a t a = ? 40 c to +85 c 2.4 mv b t a = ? 40 c to +125 c 2.8 mv b input offset voltage drift t a = 25 c, no-load 1.5 v/ c b t a = ? 40 c to +125 c 13 v/ c b
12 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics: 5 v (continued) test conditions unless otherwise noted: t a = 25 c, v s+ = 5 v, v s ? = 0 v, v cm = 1.25 v, r l = 1 k , and output is biased to midsupply (1) . parameter test conditions min typ max unit test level (2) (4) maximum bias current specification is set using 5 limits (corresponding to 0.58 dppm) obtained using the statistical distribution from electrical characterization over temperature of a sample set of 70 units. maximum specification is not specified by final automated test equipment (ate) nor by qa sample testing. (5) change in input offset from its value when input is biased to 0 v. (6) change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +psrr and -psrr. input bias current t a = 25 c 2 20 pa a t a = ? 40 c to +85 c (4) 20 50 pa b t a = ? 40 c to +125 c (4) 100 340 pa b input offset current t a = 25 c 1 20 pa a t a = ? 40 c to +85 c 5 pa b t a = ? 40 c to +125 c 50 pa b cmrr common-mode rejection ratio f = dc, t a = 25 c, v cm = 0.75 v to 1.75 v 78 92 db a t a = ? 40 c to +125 c 75 db b input allowable input differential voltage see figure 57 5 v c common-mode input impedance in closed-loop configuration 12 || 2.5 g ||pf c differential input capacitance in open-loop configuration 0.5 pf c most positive input voltage v os < 5 mv (5) v s+ + 0.2 v s+ + 0.3 v a t a = ? 40 c to +125 c v s+ + 0.2 v b most negative input voltage v os < 5 mv (5) v s- ? 0.2 v s- ? 0.3 v a t a = ? 40 c to +125 c v s- ? 0.2 v b most positive input voltage for main-jfet stage t = 25 c (see figure 43 ) v s+ ? 2.9 v s+ ? 2.5 v c t a = ? 40 c to +125 c v s+ ? 3 v c output v ocrh output voltage range high t a = 25 c, r l = 667 v s+ ? 0.12 v s+ ? 0.09 v a t a = ? 40 c to +125 c, r load = 667 v s+ ? 0.15 v b v ocrl output voltage range low t a = 25 c, r l = 667 v s ? + 0.1 v s ? + 0.06 v a t a = ? 40 c to +125 c, r l = 667 v s ? + 0.15 v b i o(max) linear output drive (sourcing and sinking) t a = 25 c, v o = 1.4 v, r l = 27.5 , v os < 2 mv, v s+ = 3 v and v s ? = ? 2 v 50 64 ma a t a = -40 c to 125 c, v o = 1.4v, r l = 27.5 , v os < 2 mv, v s+ = 3 v and v s ? = ? 2 v 40 ma b i sc output short-circuit current t a = 25 c, t delay = 5 ms 91 96 ma b c l capacitive load drive < 1 db peaking, r s = 0 ? 35 pf c power supply v s operating voltage t a = 25 c 4.75 27 v a t a = ? 40 c to +125 c 4.75 27 v b i q quiescent current per channel t a = 25 c 3.05 3.6 4 ma a t a = ? 40 c to +125 c 2.8 4.4 ma b psrr power supply rejection ratio v s = 0.5 v (6) 80 100 db a t a = ? 40 c to +125 c 80 db b
13 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated electrical characteristics: 5 v (continued) test conditions unless otherwise noted: t a = 25 c, v s+ = 5 v, v s ? = 0 v, v cm = 1.25 v, r l = 1 k , and output is biased to midsupply (1) . parameter test conditions min typ max unit test level (2) auxiliary cmos input stage gain-bandwidth product v cm = v s+ ? 1 v 35 mhz c open-loop voltage gain v cm = v s+ ? 1 v, f = dc, v o = 2 v to 4 v 80 100 db a input-referred voltage noise v cm = v s+ ? 1 v, f = 1 mhz 21 nv/ hz c input offset voltage v cm = v s+ ? 1.5 v, no-load 4 mv a v cm = v s+ ? 0.5 v, no-load 4.8 mv a v cm = v s+ ? 0.5 v, t a = ? 40 c to +125 c, no-load 6.4 mv b input bias current v cm = v s+ ? 1.5 v 2 20 pa a v cm = v s+ ? 1.5 v, t a = ? 40 c to +125 c 0.15 0.5 na b common-mode rejection ratio v cm = v s+ ? 1.5 v to v s+ ? 0.5 v 75 db b power supply rejection ratio v cm = v s+ ? 1.5 v, v s = 0.5 v (6) 75 db b channel matching channel-to-channel gbwp mismatch t a = 25 c 3 % c channel-to-channel crosstalk f = 100 khz -93 dbc c input offset voltage mismatch t a = 25 c 0.1 2.5 mv a
14 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.8 typical characteristics: v s = 10 v at v s+ = 5 v, v s ? = ? 5 v, r l = 1 k , input and output are biased to midsupply, and t a 25 c. for ac specifications, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) see figure 65 and figure 66 , v o = 20 mv pp figure 1. small-signal frequency response vs gain see figure 65 , v o = 20 mv pp , gain = 1 v/v, r f = 0 figure 2. small-signal frequency response vs output load see figure 65 , v o = 20 mv pp , gain = 2 v/v figure 3. small-signal frequency response vs output load see figure 65 and figure 63 , v o = 20 mv pp , gain = 1 v/v, r f = 0 figure 4. small-signal frequency response vs c l see figure 65 and figure 63 , v o = 20 mv pp , gain = 2 v/v figure 5. small-signal frequency response vs c l see figure 65 , gain = 1 v/v, r f = 0 figure 6. large-signal frequency response vs output voltage frequency (mhz) normalized gain (db) -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d041 gain = -1 v/v gain = 1 v/v gain = 2 v/v gain = 5 v/v gain = 10 v/v gain = 100 v/v frequency (hz) normalized gain (db) -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d042 r l = 500 : r l = 1 k : r l = 100 k : frequency (hz) normalized gain (db) -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d043 r l = 500 : r l = 1 k : r l = 100 k : frequency (hz) normalized gain (db) -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d044 r s = 0 : , c l = 2.2 pf r s = 0 : , c l = 33 pf r s = 24 : , c l = 47 pf r s = 24 : , c l = 100 pf r s = 17.4 : , c l = 200 pf frequency (hz) normalized gain (db) -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d046 v o = 200 mv pp v o = 1 v pp v o = 2 v pp v o = 4 v pp frequency (hz) normalized gain (db) -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d045 r s = 0 : , c l = 2.2pf r s = 0 : , c l = 33pf r s = 30 : , c l = 47pf r s = 30 : , c l = 100 pf r s = 23 : , c l = 200 pf
15 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics: v s = 10 v (continued) at v s+ = 5 v, v s ? = ? 5 v, r l = 1 k , input and output are biased to midsupply, and t a 25 c. for ac specifications, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) see figure 65 , gain = 2 v/v figure 7. large-signal frequency response vs output voltage see figure 65 and figure 66 , v o = 20 mv pp figure 8. small-signal response flatness vs gain see figure 65 , gain = 2 v/v figure 9. harmonic distortion vs frequency see figure 66 , gain = ? 1 v/v figure 10. harmonic distortion vs frequency see figure 65 and figure 66 , r f = 0 for gain = 1 v/v figure 11. harmonic distortion vs gain see figure 65 , gain = 1 v/v, r f = 0 figure 12. small-signal transient response frequency (hz) harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 100k 1m d050 hd2, gain = 1 hd3, gain = 1 hd2, gain = 2 hd3, gain = 2 hd2, gain = -1 hd3, gain = -1 time (200 nsec/div) output voltage (v) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 d052 frequency (hz) harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 100k 1m d048 hd2, r l = 1 k : hd3, r l = 1 k : hd2, r l = 500 : hd3, r l = 500 : frequency (mhz) normalized gain (db) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 100k 1m 10m 100m d051 gain = -1 v/v gain = 1 v/v gain = 2 v/v gain = 5 v/v gain = 10 v/v frequency (hz) normalized gain (db) -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d047 v o = 200 mv pp v o = 1 v pp v o = 2 v pp v o = 4 v pp frequency (hz) harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 100k 1m d049 hd2, r l = 1 k : hd3, r l = 1 k : hd2, r l = 500 : hd3, r l = 500 :
16 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics: v s = 10 v (continued) at v s+ = 5 v, v s ? = ? 5 v, r l = 1 k , input and output are biased to midsupply, and t a 25 c. for ac specifications, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) see figure 65 , gain = 1 v/v, r f = 0 figure 13. overshoot and undershoot vs c l see figure 65 , gain = 1 v/v, r f = 0 figure 14. input overdrive recovery see figure 66 , gain = -1 v/v figure 15. output overdrive recovery figure 16. output voltage vs load current output saturated and then short-circuited, i o measured after t delay = 5 msec figure 17. output short-circuit current vs ambient temperature measured for 34 units figure 18. input offset voltage vs input common-mode voltage output current (ma) output voltage (v) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 d056 sourcing sinking input common-mode voltage (v) input offset voltage ( p v) -6 -4 -2 0 2 4 6 -1200 -800 -400 0 400 800 1200 d058 time (ns) input and output voltage (v) 0 150 300 450 600 750 900 1050 1200 1350 1500 -6 -4 -2 0 2 4 6 d055 v in x -1 gain v o ambient temperature ( o c) output short-circuit current (ma) -50 -30 -10 10 30 50 70 90 110 130 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 d057 time (ns) input and output voltage (v) 0 150 300 450 600 750 900 1050 1200 1350 1500 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 d054 v in v o load capacitance (pf) overshoot/undershoot (%) 0 10 20 30 40 50 10 100 d053 overshoot, v o = 200 mv pp undershoot, v o = 200 mv pp overshoot, v o = 2 v pp undershoot, v o = 2 v pp
17 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.9 typical characteristics: v s = 24 v at v s+ = 12 v, v s ? = ? 12 v, r l = 1 k , input and output are biased to midsupply, and t a 25 c. for ac specifications, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) see figure 65 and figure 66 , v o = 20 mv pp figure 19. noninverting small-signal frequency response vs gain see figure 65 , v o = 20 mv pp , gain = 1 v/v, c l = 33 pf, r f = 0 figure 20. small-signal frequency response vs output common-mode voltage see figure 65 , v o = 20 mv pp , gain = 1 v/v, c l = 47 pf, r f = 0 figure 21. small-signal frequency response vs output common-mode voltage see figure 65 , gain = 1 v/v, r f = 0 figure 22. large-signal frequency response vs output voltage see figure 65 , gain = 2 v/v figure 23. large-signal frequency response vs v o see figure 65 , gain = 2 v/v figure 24. harmonic distortion vs frequency vs v o frequency harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 100k 1m d076 hd2, v o = 2 v pp hd3, v o = 2 v pp hd2, v o = 10 v pp hd3, v o = 10 v pp hd2, v o = 20 v pp hd3, v o = 20 v pp frequency (hz) normalized gain (db) -21 -18 -15 -12 -9 -6 -3 0 3 6 100k 1m 10m 100m d073 v cm = -11 v v cm = -9 v v cm = 0 v v cm = 9 v v cm = 11 v frequency (hz) normalized gain (db) -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d074 v o = 200 mv pp v o = 1 v pp v o = 2 v pp v o = 4 v pp frequency (hz) normalized gain (db) -21 -19.5 -18 -16.5 -15 -13.5 -12 -10.5 -9 -7.5 -6 -4.5 -3 -1.5 0 1.5 3 100k 1m 10m 100m d071 gain = -1 v/v gain = 1 v/v gain = 2 v/v gain = 5 v/v frequency (hz) normalized gain (db) -21 -18 -15 -12 -9 -6 -3 0 3 6 100k 1m 10m 100m d072 v cm = -11 v v cm = -9 v v cm = 0 v v cm = 9 v v cm = 11 v frequency (hz) normalized gain (db) -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d075 v o = 200 mv pp v o = 1 v pp v o = 2 v pp v o = 4 v pp v o = 10 v pp
18 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics: v s = 24 v (continued) at v s+ = 12 v, v s ? = ? 12 v, r l = 1 k , input and output are biased to midsupply, and t a 25 c. for ac specifications, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) see figure 66 , gain = ? 1 v/v figure 25. harmonic distortion vs frequency vs v o see figure 65 , gain = 1 v/v, r f = 0 figure 26. small-signal transient response see figure 65 , gain = 1 v/v, r f = 0 figure 27. large-signal transient response see figure 65 , gain = 2 v/v figure 28. large-signal transient response see figure 66 , gain = ? 1 v/v figure 29. large-signal transient response see figure 65 , gain = 1 v/v, r f = 0 figure 30. overshoot and undershoot vs c l time (200 nsec/div) output voltage (v) 500 700 900 1100 1300 1500 1700 1900 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 d078 time (200 ns/div) output voltage (v) -6 -4 -2 0 2 4 6 d081 v o = 2 v pp v o = 10 v pp frequency (hz) harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 100k 1m d077 hd2, v o = 2 v pp hd3, v o = 2 v pp hd2, v o = 10 v pp hd3, v o = 10 v pp hd2, v o = 20 v pp hd3, v o = 20 v pp time (200 ns/div) output voltage (v) 300 500 700 900 1100 1300 -6 -4 -2 0 2 4 6 d079 v o = 2 v pp v o = 10 v pp time (200 ns/div) output voltage (v) -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 d080 v o = 2 v pp v o = 10 v pp v o = 20 v pp load capacitance (pf) overshoot/undershoot (%) 0 10 20 30 40 50 10 100 d082 overshoot, v o = 200 mv pp undershoot, v o = 200 mv pp overshoot, v o = 2 v pp undershoot, v o = 2 v pp
19 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics: v s = 24 v (continued) at v s+ = 12 v, v s ? = ? 12 v, r l = 1 k , input and output are biased to midsupply, and t a 25 c. for ac specifications, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) see figure 65 , gain = 1 v/v, r f = 0 figure 31. input overdrive recovery see figure 66 , gain = ? 1 v/v figure 32. output overdrive recovery figure 33. output voltage range vs load current output saturated and then short-circuited, i o measured after t delay = 5 msec figure 34. output short-circuit current vs ambient temperature measured for 34 units figure 35. input offset voltage vs input common-mode voltage input common-mode voltage (v) input offset voltage ( p v) -12.5 -10 -7.5 -5 -2.5 0 2.5 5 7.5 10 12.5 -1500 -1000 -500 0 500 1000 1500 d087 output current (ma) output voltage (v) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 d085 sourcing sinking time (ns) input and output voltage (v) 0 150 300 450 600 750 900 1050 1200 1350 1500 -15 -12 -9 -6 -3 0 3 6 9 12 15 d084 v in x -1 gain v o ambient temperature ( o c) output short-circuit current (ma) -50 -30 -10 10 30 50 70 90 110 130 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 d086 time (ns) input and output voltage (v) 0 150 300 450 600 750 900 1050 1200 1350 1500 -15 -12 -9 -6 -3 0 3 6 9 12 15 d083 v in v o
20 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.10 typical characteristics: v s = 5 v at v s+ = 5 v, v s ? = 0 v, v cm = 1.25 v, r l = 1 k , output is biased to midsupply, and t a 25 c. for ac specifications, v s+ = 3.5 v, v s ? = ? 1.5 v, v cm = 0 v, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) see figure 65 and figure 66 , v o = 20 mv pp figure 36. small-signal response vs gain see figure 65 , gain = 1 v/v, r f = 0 figure 37. small-signal transient response see figure 65 , gain = 1 v/v, r f = 0 figure 38. overshoot and undershoot vs c l see figure 65 , gain = 1 v/v, r f = 0 figure 39. input overdrive recovery see figure 66 , gain = ? 1 v/v figure 40. output overdrive recovery figure 41. output voltage range vs output current frequency (hz) normalized gain (db) -21 -19.5 -18 -16.5 -15 -13.5 -12 -10.5 -9 -7.5 -6 -4.5 -3 -1.5 0 1.5 3 100k 1m 10m 100m d010 gain = -1 v/v gain = 1 v/v gain = 2 v/v gain = 5 v/v time (200 nsec/div) output voltage (v) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 d011 time (ns) input and output voltage (v) 0 150 300 450 600 750 900 1050 1200 1350 1500 -4 -3 -2 -1 0 1 2 3 4 d014 v in x -1 gain v o load capacitance (pf) overshoot/undershoot (%) 0 10 20 30 40 50 10 100 d012 overshoot, v o = 200 mv pp undershoot, v o = 200 mv pp overshoot, v o = 2 v pp undershoot, v o = 2 v pp output current (ma) output voltage (v) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 -3 -2 -1 0 1 2 3 d015 sourcing sinking time (ns) input and output voltage (v) 0 150 300 450 600 750 900 1050 1200 1350 1500 -4 -3 -2 -1 0 1 2 3 4 d013 v in v o
21 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics: v s = 5 v (continued) at v s+ = 5 v, v s ? = 0 v, v cm = 1.25 v, r l = 1 k , output is biased to midsupply, and t a 25 c. for ac specifications, v s+ = 3.5 v, v s ? = ? 1.5 v, v cm = 0 v, v o = 2 v pp , g = 2 v/v, r f = 1 k , and c l = 4.7 pf (unless otherwise noted) output saturated and then short-circuited, i o measured after t delay = 5 msec figure 42. output short-circuit current vs ambient temperature measured for 34 units figure 43. input offset voltage vs input common-mode voltage input common-mode voltage (v) input offset voltage ( p v) -3 -2 -1 0 1 2 3 -1000 -500 0 500 1000 d017 ambient temperature ( o c) output short-circuit current (ma) -50 -30 -10 10 30 50 70 90 110 130 50 60 70 80 90 100 110 120 130 d016
22 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 6.11 typical characteristics: 2.375 v to 12 v split supply at v o = 2 v pp , r f = 1 k , r l = 1 k and t a 25 c (unless otherwise noted) simulated with no output load figure 44. open-loop gain and phase vs frequency see figure 65 , gain = 1 v/v, r f = 0 figure 45. large-signal response vs supply voltage see figure 65 , gain = 2 v/v figure 46. large-signal response vs supply voltage see figure 65 , gain = 2 v/v figure 47. harmonic distortion vs frequency vs supply voltage see figure 66 , gain = ? 1 v/v figure 48. harmonic distortion vs frequency vs supply voltage measured then fit to ideal 1/f model figure 49. input voltage noise density vs frequency frequency (hz) harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 100k 1m d104 hd2, v s = 5 v hd3, v s = 5 v hd2, v s = 10 v hd3, v s = 10 v hd2, v s = 24 v hd3, v s = 24 v frequency (hz) input voltage noise (nv/ ? hz) 1 10 100 1000 10 100 1k 10k 100k 1m 10m d105 frequency (hz) normalized gain (db) -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d102 v s = 5 v v s = 10 v v s = 24 v frequency (hz) harmonic distortion (dbc) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 100k 1m d103 hd2, v s = 5 v hd3, v s = 5 v hd2, v s = 10 v hd3, v s = 10 v hd2, v s = 24 v hd3, v s = 24 v frequency (hz) normalized gain (db) -21 -18 -15 -12 -9 -6 -3 0 3 100k 1m 10m 100m d101 v s = 5 v v s = 10 v v s = 24 v frequency (hz) open-loop gain magnitude (db) open-loop phase ( o ) -10 40 10 60 30 80 50 100 70 120 90 140 110 160 130 180 10 100 1k 10k 100k 1m 10m 100m d109 magnitude phase
23 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics: 2.375 v to 12 v split supply (continued) at v o = 2 v pp , r f = 1 k , r l = 1 k and t a 25 c (unless otherwise noted) measured then fit to ideal 1/f model figure 50. auxiliary input stage voltage noise density vs frequency see figure 65 , gain = 1 v/v, r f = 0 figure 51. crosstalk vs frequency see figure 65 (simulation) figure 52. closed-loop output impedance vs frequency simulated curves figure 53. common-mode rejection ratio vs frequency simulated curves, v s = 5 v and 10 v figure 54. power supply rejection ratio vs frequency simulated curves, v s = 24 v figure 55. power supply rejection ratio vs frequency frequency (hz) crosstalk (dbc) -140 -120 -100 -80 -60 -40 100k 1m 10m 100m d107 ch-a to ch-b ch-b to ch-a frequency (hz) common-mode rejection ratio (db) 20 30 40 50 60 70 80 90 100 110 120 100 1k 10k 100k 1m 10m 100m d110 v s = 5 v v s = 10 v v s = 24 v frequency (hz) aux input voltage noise (nv/ ? hz) 10 100 1000 10000 10 100 1k 10k 100k 1m 10m d106 frequency (hz) power supply rejection ratio (db) 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m 100m d112 psrr v s+ psrr v s- frequency (hz) output impedance (ohms) 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m d108 gain = 1 v/v gain = 2 v/v frequency (hz) power supply rejection ratio (db) 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m 100m d111 psrr v s+ psrr v s-
24 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated typical characteristics: 2.375 v to 12 v split supply (continued) at v o = 2 v pp , r f = 1 k , r l = 1 k and t a 25 c (unless otherwise noted) v s = 12-v figure 56. input bias current vs input common-mode voltage abs (v in,diff (max) ) = v s when v s < 7 v figure 57. input bias current vs differential input voltage 70 units, dgk package figure 58. quiescent current vs ambient temperature 70 units, dgk package figure 59. input offset voltage vs ambient temperature input offset voltage ( v), 1246 units figure 60. input offset voltage distribution input offset voltage drift ( v/ c), ? 40 c to +125 c fit, 70 units figure 61. input offset voltage drift distribution no. of units in each bin 0 2 4 6 8 10 12 14 16 18 -7 -6 -5 -4 -3 -2 -1 01 2 3 4 5 6 7 d114 ambient temperature ( o c) input offset voltage ( p v) -40 -20 0 20 40 60 80 100 120 -600 -400 -200 0 200 400 600 d116 ambient temperature ( o c) quiescent current (ma) -40 -20 0 20 40 60 80 100 120 3.45 3.55 3.65 3.75 3.85 d117 no. of units in each bin 0 50 100 150 200 250 300 -400 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 400 d113 differential input voltage (v) non-inverting input bias current ( p a) -7.5 -6 -4.5 -3 -1.5 0 1.5 3 4.5 6 7.5 -300 -200 -100 0 100 200 300 d115 t a = 25 o c t a = 125 o c input common-mode voltage (v) inverting input bias current (pa) -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 -10 -8 -6 -4 -2 0 2 4 6 8 10 d118
25 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7 detailed description 7.1 overview the opa2810 is a dual-channel, fet-input, unity-gain stable voltage-feedback operational amplifier with extremely low input bias current across its common-mode input voltage range. the opa2810, characterized to operate over a wide supply range of 4.75 v to 27 v, has a small-signal unity-gain bandwidth of 105 mhz and offers both excellent dc precision and dynamic ac performance at low quiescent power. the opa2810 is fabricated on texas instrument's proprietary, high-speed sige bicmos process and achieves significant performance improvements over comparable fet-input amplifiers at similar levels of quiescent power. with a gain-bandwidth product (gbwp) of 70mhz, extremely high slew-rate (192 v/ s), and low-noise (6 nv/ hz) the opa2810 is ideal in a wide range of data acquisition and signal processing applications. the opa2810 includes input clamps to allow maximum input differential voltage of up to 7 v, making it suitable for use with multiplexers and processing of signals with fast transients. it achieves these benchmark levels of performance while consuming a typical quiescent current (i q ) of 3.6 ma /channel. the opa2810 can source and sink large amounts of current without degradation in its linearity performance. the wide-bandwidth of the opa2810 implies that the device has low output-impedance across a wide frequency range, thereby allowing the amplifier to drive capacitive loads up to 35 pf without requiring output isolation. this device is suitable for a wide range of data acquisition, test and measurement front-end buffer, impedance measurement, power analyzer, wideband photodiode transimpedance and signal processing applications. 7.2 functional block diagram the opa2810 features a true high-impedance input stage including a jfet differential-input pair main stage and a cmos differential-input auxiliary (aux) stage operational within 2.5 v of the positive supply voltage. the bias current is limited to a maximum of 20 pa throughout the common-mode input range of the amplifier. figure 62 shows a block diagram representation for the input stage of the opa2810. figure 62. input-stage block diagram aux-stage v s+ en jfet-stage v s- en v s+ 2.5 v v in(1,2)+ v in(1,2)- v o(1,2) + + + opa2810 c c
26 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated functional block diagram (continued) the amplifier exhibits superior performance for high-speed signals (distortion, noise and input offset voltage) while the aux stage enables rail-to-rail inputs and prevents phase reversal. the opa2810 also includes input clamps which enable maximum input differential voltage of upto 7 v (lower of 7 v and total supply voltage). this architecture offers significantly greater differential input voltage capability as compared to one to two times the diode forward voltage drop maximum rating in standard amplifiers, and makes this device suitable for use with multiplexers and processing of signals with fast transients. the input bias currents are also clamped to maximum 300 a, as figure 57 shows, which does not load the previous driver stage or require current-limiting resistors (except limiting current through the input esd diodes when input common-mode voltages are greater than the supply voltages). this also enables the use of one of the channels as a comparator in systems which require an amplifier and a comparator for signal-gain and fault-detection, respectively. for the lowest offset, distortion and noise performance, limit the common-mode input voltage to the main jfet-input stage (greater than 2.5 v away from the positive supply). the opa2810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in figure 16 for 10-v supply operation. this is particularly useful for inputs biased near the rails or when the amplifier is configured in a closed-loop gain such that the output approaches the supply voltage. when the output saturates, it recovers with 55 ns when inputs exceed the supply voltages by 0.5 v in an g = ? 1 v/v inverting gain with a 10 ? v supply. the outputs are short-circuit protected with the limits of figure 17 . an amplifier phase margin reduces and it becomes unstable when driving a capacitive load (c l ) at the output, as figure 63 shows. use of a series resistor (r s ) between the amplifier output and load capacitance introduces a zero which cancels the pole formed by the amplifier output impedance and c l in the open-loop transfer function. the opa2810 drives capacitive loads of up to 35 pf without causing instability. it is recommended to use a series resistor for larger load capacitance values, as figure 4 shows for opa2810 configured as a unity-gain buffer. figure 63. opa2810 driving capacitive load 7.2.1 esd protection all the device pins are protected with internal esd protection diodes to the power supplies as figure 64 shows. these diodes provide moderate protection to input overdrive voltages above the supplies . the protection diodes can typically support 10-ma continuous input and output currents. the differential input clamps only limit the bias current when the input common-mode voltages are within the supply voltage range, whereas current limiting series resistors must be added at the inputs if common-mode voltages higher than the supply voltages are possible. keep these resistor values as low as possible because using high values degrades noise performance and frequency response. figure 64. internal esd protection + r s r l c l v in v o + v s+ v s- v in(1,2)+ v o(1,2) power supply esd cell v in(1,2)- 300 a i clamp
27 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 7.3 feature description 7.3.1 opa2810 comparison table 1 lists several members of the device family that includes the opa2810. table 1. related operational amplifier products device v s (v) i q / channel (ma) gbwp (mhz) slew rate (v/ s) voltage noise (nv/ hz) amplifier description opa2810 12 3.6 70 192 6 unity-gain stable fet input (dual-ch) ths4631 15 13 210 900 7 unity-gain stable fet input opa656 6 14 230 290 7 unity-gain stable fet input opa657 6 14 1600 700 4.8 gain of 7 stable fet input opa659 6 32 350 2550 8.9 unity-gain stable fet input 7.4 device functional modes 7.4.1 split-supply operation ( 2.375 v to 13.5 v) to facilitate testing with common lab equipment, the opa2810 can be configured to allow for split-supply operation (see opa2810dgk evaluation module ). this configuration eases lab testing because the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers and other lab equipment reference the inputs and outputs to ground. figure 65 shows the opa2810 configured as a noninverting amplifier and figure 66 shows the opa2810 configured as an inverting amplifier. for split-supply operation referenced to ground, the power supplies v s+ and v s- are symmetrical around ground and v ref = gnd. split-supply operation is preferred in systems where the signals swing around ground because of the ease-of-use; however, the system requires two supply rails. 7.4.2 single-supply operation (4.75 v to 27 v) many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply. the opa2810 can be used with a single supply (negative supply set to ground) with no change in performance if the input and output are biased within the linear operation of the device. to change the circuit from split supply to a balanced, single-supply configuration, level shift all the voltages by half the difference between the power-supply rails. an additional advantage of configuring an amplifier for single-supply operation is that the effects of psrr are minimized because the low-supply rail is grounded. see single-supply op amp design techniques application report for examples of single-supply designs.
28 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information 8.1.1 selection of feedback resistors the opa2810 is a classic voltage feedback amplifier with each channel having two high-impedance inputs and a low-impedance output. standard application circuits include the noninverting and inverting gain configurations as figure 65 and figure 66 show. the dc operating point for each configuration is level-shifted by the reference voltage v ref which is typically set to midsupply in single-supply operation. v ref is often connected to ground in split-supply applications. figure 65. noninverting amplifier figure 66. inverting amplifier the closed-loop gain of an amplifier in noninverting configuration is shown in equation 1 . (1) the closed-loop gain of an amplifier in an inverting configuration is shown in equation 2 . (2) the magnitude of the low-frequency gain is determined by the ratio of the magnitudes of the feedback resistor (r f ) and the gain setting resistor r g . the order of magnitudes of the individual values of r f and r g offer a trade- off between amplifier stability, power dissipated in the feedback resistor network, and total output noise. the feedback network increases the loading on the amplifier output. using large values of the feedback resistors reduces the power dissipated at the amplifier output. on the other hand, this increases the inherent voltage and ? ? 1 f o in ref g r v v v r + v in r g v ref v ref r f v sig v ref (1+r f /r g )v sig v o v s+ v s- + v in r g v ref v ref r f v sig v ref -(r f /r g )v sig v o v s+ v s- ? ? 1 f o in ref g r v v 1 v r
29 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) amplifier current noise contribution seen at the output while lowering the frequency at which a pole occurs in the feedback factor ( ). this pole causes a decrease in the phase margin at zero-gain crossover frequency and potential instability. using small feedback resistors increases power dissipation and also degrades amplifier linearity due to a heavier amplifier output load. figure 67 shows a representative schematic of the opa2810 in an inverting configuration with the input capacitors shown. figure 67. inverting amplifier with input capacitors the effective capacitance seen at the amplifier's inverting input pin is shown in equation 3 which forms a pole in at a cut-off frequency of equation 4 . (3) (4) where: ? c cm is the amplifier common-mode input capacitance ? c diff is the amplifier differential input capacitance ? and, c pcb is the pcb parasitic capacitance. for low-power systems, greater the values of the feedback resistors, the earlier in frequency does the phase margin begin to reduce and cause instability. figure 68 and figure 69 show the loop gain magnitude and phase plots, respectively, for the opa2810 simulation in tina-ti configured as an inverting amplifier with values of feedback resistors varying by orders of magnitudes. figure 68. loop-gain vs. frequency for circuit of figure 67 s c f in 1 f 2 r c c diff + v in r g v ref r f v sig v ref -(r f /r g )v sig v o v s+ v s- c cm c cm c pcb in cm diff pcb c c c c frequency (hz) gain (db) -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 100 1k 10k 100k 1m 10m 100m d801 r f = 200 : , r g = 50 : r f = 10 k : , r g = 2.5 k : r f = 1 m : , r g = 250 k :
30 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) figure 69. loop-gain phase vs. frequency for circuit of figure 67 a lower phase margin results in peaking in the frequency response and lower bandwidth as figure 70 shows, which is synonymous with overshoot and ringing in the pulse response results. the opa2810 offers a flat-band voltage noise density of 6 nv/ hz. it is recommended to select an r f so the voltage noise contribution does not exceed that of the amplifier. figure 71 shows the voltage noise density variation with value of resistance at 25 c. a 2-k resistor exhibits a thermal noise density of 5.75 nv/ hz which is comparable to the flatband noise of the opa2810. hence, it is recommended to use an r f lower than 2 k while being large enough to not dissipate excessive power for the output voltage swing and supply current requirements of the application. the noise analysis and the effect of resistor elements on total noise section shows a detailed analysis of the various contributors to noise. figure 70. closed-loop gain vs. frequency for circuit of figure 67 figure 71. thermal noise density vs resistance frequency (hz) gain (db) -10 0 10 20 30 10k 100k 1m 10m 100m d806 r f = 200 : , r g = 50 : r f = 10 k : , r g = 2.5 k : r f = 1 m : , r g = 250 k : resistance ( : ) voltage noise density (nv/ ? hz) 0.1 1 10 100 1000 10 100 1k 10k 100k 1m 10m d803 frequency (hz) phase (degrees) 0 10 20 30 40 50 60 70 80 90 100 100 1k 10k 100k 1m 10m 100m d802 r f = 200 : , r g = 50 : r f = 10 k : , r g = 2.5 k : r f = 1 m : , r g = 250 k :
31 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) 8.1.2 noise analysis and the effect of resistor elements on total noise the opa2810 provides a low input-referred broadband noise voltage density of 6 nv/ hz while requiring a low 3.6-ma quiescent supply current. to take full advantage of this low input noise, careful attention to the other possible noise contributors is required. figure 72 shows the operational amplifier noise analysis model with all the noise terms included. in this model, all the noise terms are taken to be noise voltage or current density terms in nv/ hz or pa/ hz. figure 72. operational amplifier noise analysis model the total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. this computation adds all the contributing noise powers at the output by superposition, then calculates the square root to get back to a spot noise voltage. figure 72 shows the general form for this output noise voltage using the terms shown in equation 5 . (5) dividing this expression by the noise gain (ng = 1 + r f / r g ) shows the equivalent input referred spot noise voltage at the noninverting input; see equation 6 . (6) substituting large resistor values into equation 6 can quickly dominate the total equivalent input referred noise. a source impedance on the noninverting input of 2-k adds a johnson voltage noise term equal to that of the amplifier (6 nv/ hz). table 2 compares the noise contributions from the various terms when the opa2810 is configured in a noninverting gain of 5v/v as figure 73 shows. two cases are considered where the resistor values in case 2 are 10x the resistor values in case 1. the total output noise in case 1 is 31.3 nv/ hz while the noise in case 2 is 49.7 nv/ hz. the large value resistors in case 2 dilute the benefits of selecting a low noise amplifier like the opa2810. to minimize total system noise, reduce the size of the resistor values. this increases the amplifiers output load and results in a degradation of distortion performance. the increased loading increases the dynamic power consumption of the amplifier. the circuit designer must make the appropriate tradeoffs to maximize the overall performance of the amplifier to match the system requirements. ( ) 2 2 2 bi f f n ni bn s s i r 4ktr e e i r 4ktr ng ng ? ? = + + + + ? ? + r s e rs r f r g i bn e ni i bi e o s 4ktr g 4kt r f 4ktr 4kt 1.6e 20 j at 290 k q ( ) ( ) ( ) 2 2 2 2 o ni bn s s f e e i r 4ktr ng i r 4ktr ng bi f = + + + +
32 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated application information (continued) figure 73. comparing noise contributors for two cases with the amplifier in a noninverting gain of 5 v/v table 2. comparing noise contributions for the circuit in figure 73 noise source output noise equation case1 case2 noise source value voltage noise contribution (nv/ hz) noise power contribution (nv 2 /hz) contribution (%) noise source value voltage noise contribution (nv/ hz) noise power contribution (nv 2 /hz) contribution (%) source resistor, r s e rs (1+r f /r g ) 1.82 nv/ hz 9.1 82.81 7.77 5.76 nv/ hz 28.8 829.44 32.41 gain resistor, r g e rg (r f /r g ) 2.04 nv/ hz 8.16 66.59 6.24 6.44 nv/ hz 25.76 663.58 25.93 feedback resistor, r f e rf 4.07 nv/ hz 4.07 16.57 1.55 12.87 nv/ hz 12.87 165.64 6.47 amplifier voltage noise, e ni e ni (1+r f /r g ) 6 nv/ hz 30 900 84.43 6 nv/ hz 30 900 35.17 inverting current noise, i bi i bi (r f ||r g ) 5 fa/ hz 5.0e-3 ? ? 5 fa/ hz 50e-3 ? ? noninverting current noise, i bn i bn r s (1+r f /r g ) 5 fa/ hz 1.0e-3 ? ? 5 fa/ hz 10e-3 ? ? case1: 200 case2: 2 k e o + v s+ = 5v v s- = -5v r s r g r f case1: 250 case2: 2.5 k case1: 1 k case2: 10 k
33 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.2 typical applications 8.2.1 transimpedance amplifier the high gbwp and low input voltage and current noise for the opa2810 make it an ideal wideband transimpedance amplifier for moderate to high transimpedance gains. figure 74. wideband, high-sensitivity, transimpedance amplifier 8.2.1.1 design requirements design a high-bandwidth, high-gain transimpedance amplifier with the design requirements listed in table 3 . table 3. design requirements target bandwidth (mhz) transimpedance gain (k ) photodiode capacitance (pf) > 2 100 20 8.2.1.2 detailed design procedure designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit from the low input voltage noise of the opa2810. this input voltage noise is peaked up over frequency by the diode source capacitance, and can, in many cases, become the limiting factor to input sensitivity. the key elements to the design are the expected diode capacitance (c d ) with the reverse bias voltage (v bias ) applied, the desired transimpedance gain, r f , and the gbwp for the opa2810 (70 mhz). figure 74 shows a transimpedance circuit with the parameters as described in table 3 . with these three variables set (and including the parasitic input capacitance for the opa2810 and the pcb added to c d ), the feedback capacitor value (c f ) may be set to control the frequency response. transimpedance considerations for high-speed amplifiers discusses using high-speed amplifiers for transimpedance applications. to achieve a maximally-flat second-order butterworth frequency response, set the feedback pole to: (7) the input capacitance of the amplifier is the sum of the common-mode and differential capacitance (2.5 + 0.5) pf. the parasitic capacitance from the photodiode package and the pcb is approximately 0.3 pf. using equation 3 , this results in a total input capacitance of c d = 23.3 pf. from equation 7 , set the feedback pole at 1.55 mhz. setting the pole at 1.55 mhz requires a total feedback capacitance of 1.03 pf. the approximate ? 3-db bandwidth of the transimpedance amplifier circuit is shown in: (8) v bias + c d 20 pf c pcb 0.3 pf opa2810 +5 v -5 v c f + c pcb 1.03 pf r s 50 oscilloscope with 50 inputs r f 100 k supply decoupling not shown 1 2 4 f f f d gbwp r c r c s s 3 / (2 ) db f d f gbwp r c hz s
34 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated equation 8 estimates a closed-loop bandwidth of 2.19 mhz. figure 75 and figure 76 show the loop-gain magnitude and phase plots from the tina-ti simulations of the transimpedance amplifier circuit of figure 74 . the 1/ gain curve has a zero from r f and c in at 70 khz and a pole from r f and c f cancelling the 1/ zero at 1.5 mhz resulting in a 20 db/decade rate-of-closure at the loop gain crossover frequency (freqeuncy where a ol = 1/ ), ensuring a stable circuit. a phase margin of 62 is obtained with a closed-loop bandwidth of 3 mhz and 100- k transimpedance gain. figure 75. loop-gain magnitude vs. frequency for transimpedance amplifier circuit of figure 74 figure 76. loop-gain phase vs. frequency for transimpedance amplifier circuit of figure 74 frequency (hz) phase (degrees) 0 10 20 30 40 50 60 70 80 90 100 100 1k 10k 100k 1m 10m 100m d805 a ol 1/ e a ol e frequency (hz) gain (db) -10 0 10 20 30 40 50 60 70 80 90 100 110 120 100 1k 10k 100k 1m 10m 100m d804 a ol 1/ e a ol e
35 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 8.2.2 multichannel sensor interface high-z input amplifiers are particularly useful when interfaced with sensors that have relatively high output impedance. such multichannel systems usually interface these sensors with the signal chain through a multiplexer. figure 77 shows one such implementation using an amplifier for interface with each sensor, and driving into an adc through a multiplexer. an alternate circuit, shown in figure 78 , may use a single higher gbwp and fast-settling amplifier at the output of the multiplexer. this gives rise to large signal transients when switching between channels, where the settling performance of the amplifier and maximum allowed differential input voltage limits signal chain performance and amplifier reliability, respectively. figure 77. multichannel sensor interface using multiple amplifiers figure 78. multichannel sensor interface using a single higher gbwp amplifier figure 79 shows the output voltage and input differential voltage when a 8-v step is applied at the noninverting terminal of the opa2810 configured as a unity-gain buffer of figure 78 . figure 79. large-signal transient response using opa2810 because of the fast input transient, the amplifier is slew-limited and the inputs cease to track each other (a maximum v in,diff of 7v is seen in figure 79 ) until the output reaches its final value and the negative feedback loop is closed. for standard amplifiers with a 0.7-1.5v maximum v in,diff rating, it is required to use current-limiting resistors in series with the input pins to protect from irreversible damage, which also limits the device frequency response. the opa2810 has built-in input clamps that allow the application of as much as 7v of v in,diff , with no external resistors required and no damage to the device or a shift in performance specifications. such an input- stage architecture coupled, with its fast settling performance, makes the opa2810 a good fit for multichannel sensor multiplexed systems. mux + adc + + mux + adc opa2810 time (10 ns/div) input and output voltage (v) -5 -2.5 0 2.5 5 7.5 bd_m v in v o v in,diff
36 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 9 power supply recommendations the opa2810 is intended for operation on supplies ranging from 4.75 v to 27 v. the opa2810 may be operated on single-sided supplies, split and balanced bipolar supplies or unbalanced bipolar supplies. operating from a single supply can have numerous advantages. with the negative supply at ground, the dc errors due to the ? psrr term can be minimized. typically, ac performance improves slightly at 10-v operation with minimal increase in supply current. minimize the distance ( < 0.1") from the power supply pins to high-frequency, 0.01 uf decoupling capacitors. a larger capacitor (2.2 uf typical) is used along with a high-frequency, 0.01 uf supply- decoupling capacitor at the device supply pins. for single-supply operation, only the positive supply has these capacitors. when a split-supply is used, use these capacitors from each supply to ground. if necessary, place the larger capacitors further from the device and share these capacitors among several devices in the same area of the printed circuit board (pcb). an optional supply decoupling capacitor across the two power supplies (for split- supply operation) reduces second harmonic distortion. 10 layout 10.1 layout guidelines achieving optimum performance with a high-frequency amplifier like the opa2810 requires careful attention to board layout parasitics and external component types. the opa2810evm can be used as a reference when designing the circuit board. recommendations that optimize performance include: 1. minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability ? on the noninverting input, it can react with the source impedance to cause unintentional band-limiting. to reduce unwanted capacitance, open a window around the signal i/o pins in all of the ground and power planes around those pins. otherwise, ground and power planes must be unbroken elsewhere on the board. 2. minimize the distance ( < 0.1") from the power-supply pins to high-frequency 0.01- f decoupling capacitors. at the device pins, do not allow the ground and power plane layout to be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. the power-supply connections must always be decoupled with these capacitors. larger (2.2- f to 6.8- f) decoupling capacitors, effective at lower frequency, must also be used on the supply pins. these can be placed somewhat farther from the device and shared among several devices in the same area of the pc board. 3. careful selection and placement of external components preserve the high frequency performance of the opa2810. resistors must be a low reactance type. surface-mount resistors work best and allow a tighter overall layout. metal film and carbon composition axially leaded resistors can also provide good high frequency performance. again, keep their leads and pcb trace length as short as possible. never use wirewound type resistors in a high frequency application. because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. other network components, such as noninverting input termination resistors, must also be placed close to the package. even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. good axial metal film or surface mount resistors have approximately 0.2 pf in shunt with the resistor. for resistor values > 10 k , this parasitic capacitance can add a pole or zero close to the gbwp of 70 mhz and subsequently affects circuit operation. keep resistor values as low as possible consistent with load driving considerations. lowering the resistor values keep the resistor noise terms low, and minimize the effect of its parasitic capacitance, however lower resistor values increase the dynamic power consumption because r f and r g become part of the amplifiers output load network. transimpedance applications (see transimpedance amplifier ) can use whatever feedback resistor is required by the application as long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the inverting node. 4. connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. for short connections, consider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s for sufficient phase margin and stability. low parasitic capacitive loads ( < 35 pf) may not need an r s because the opa2810 is nominally compensated to operate with a 35-pf parasitic load. higher parasitic capacitive loads without an r s are allowed as the signal gain increases (increasing the unloaded phase margin) if a long trace is required, and the 6-db signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement
37 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated layout guidelines (continued) a matched impedance transmission line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50- environment is normally not necessary onboard, and a higher impedance environment improves distortion. with a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the opa2810 is used as well as a terminating shunt resistor at the input of the destination device. remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device ? this total effective impedance must be set to match the trace impedance. if the 6-db attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value to obtain sufficient phase margin and stability. this does not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the destination device is low, the signal attenuates because of the voltage divider formed by the series output into the terminating impedance. 5. take care to design the pcb layout for optimal thermal dissipation. for the extreme case of 125 c operating ambient, using the approximate maximum 177.2 c/w for the two packages, and an internal power of 24-v supply 9-ma 125 c supply current (both amplifiers) gives a maximum internal power dissipation of 216 mw. this power gives a 38 c increase from ambient to junction temperature. load power adds to this value and this dissipation must also be calculated to determine the worst-case safe operating point. 6. socketing a high speed part like the opa2810 is not recommended. the additional lead length and pin- to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. best results are obtained by soldering the opa2810 onto the board. 10.2 layout example figure 80. layout recommendation place bypass capacitors close to power pins place gain and feedback resistors close to pins to minimize stray capacitance place series output resistors close to output pin to minimize parasitic capacitance ground and power plane removed from inner layers. ground fill on outer layers also removed ground and power plane exist on inner layers. place bypass capacitors close to power pins remove gnd and power plane under output and inverting pins to minimize stray pcb capacitance c byp r f r g + v s- c byp v s+ representative schematic of a single channel 1 8 2 7 3 6 4 5 r s c byp c byp r f r f r g r g r s r s
38 opa2810 sbos789a ? august 2017 ? revised june 2018 www.ti.com product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 10.3 thermal considerations the opa2810 does not require heat sinking or airflow in most applications. maximum allowed junction temperature sets the maximum allowed internal power dissipation. do not allow the maximum junction temperature to exceed 150 c. operating junction temperature (t j ) is given by t a + p d ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is the specified no-load supply current times the total supply voltage across the part. p dl depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). under this condition p dl = v s 2 / (4 r l ) where r l includes feedback network loading. the power in the output stage and not into the load that determines internal power dissipation. as a worst-case example, compute the maximum t j using an opa2810-dgk (vssop package) configured as a unity gain buffer, operating on 12-v supplies at an ambient temperature of 25 c and driving a grounded 500- load. p d = 24 v 9 ma + 12 2 /(4 500 ) = 288 mw maximum t j = 25 c + (0.288 w 177.2 c/w) = 76 c, which is well below the maximum allowed junction temperature of 150 o c.
39 opa2810 www.ti.com sbos789a ? august 2017 ? revised june 2018 product folder links: opa2810 submit documentation feedback copyright ? 2017 ? 2018, texas instruments incorporated 11 device and documentation support 11.1 documentation support 11.1.1 related documentation for related documentation see the following: ? opa2810dgk evaluation module ? single-supply op amp design techniques ? transimpedance considerations for high-speed amplifiers ? blog: what you need to know about transimpedance amplifiers ? part 1 ? blog: what you need to know about transimpedance amplifiers ? part 2 ? noise analysis for high-speed op amps ? tina model and simulation tool 11.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 1-jul-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples opa2810idcnt preview sot-23 dcn 8 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 2810 opa2810idgkr active vssop dgk 8 2500 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 125 2810 opa2810idgkt active vssop dgk 8 250 green (rohs & no sb/br) cu nipdauag level-2-260c-1 year -40 to 125 2810 XOPA2810IDCNT active sot-23 dcn 8 250 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 1-jul-2018 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant opa2810idgkr vssop dgk 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 opa2810idgkt vssop dgk 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 package materials information www.ti.com 29-jun-2018 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) opa2810idgkr vssop dgk 8 2500 366.0 364.0 50.0 opa2810idgkt vssop dgk 8 250 366.0 364.0 50.0 package materials information www.ti.com 29-jun-2018 pack materials-page 2

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